<html><body><samp><pre>
<!@TC:1471584041>
#Build: Synplify Pro K-2015.09L-2, Build 126R, Dec 14 2015
#install: D:\software\diamond\3.7_x64\synpbase
#OS: Windows 7 6.1
#Hostname: D27429

# Fri Aug 19 13:20:41 2016

#Implementation: syn_results

<a name=compilerReport1></a>Synopsys HDL Compiler, version comp201509p1, Build 145R, built Dec  9 2015</a>
@N: : <!@TM:1471584041> | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

<a name=compilerReport2></a>Synopsys Verilog Compiler, version comp201509p1, Build 145R, built Dec  9 2015</a>
@N: : <!@TM:1471584041> | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"D:\software\diamond\3.7_x64\synpbase\lib\lucent\ecp5u.v"
@I::"D:\software\diamond\3.7_x64\synpbase\lib\lucent\pmi_def.v"
@I::"D:\software\diamond\3.7_x64\synpbase\lib\vlog\hypermods.v"
@I::"D:\software\diamond\3.7_x64\synpbase\lib\vlog\umr_capim.v"
@I::"D:\software\diamond\3.7_x64\synpbase\lib\vlog\scemi_objects.v"
@I::"D:\software\diamond\3.7_x64\synpbase\lib\vlog\scemi_pipes.svh"
@I::"D:\software\diamond\3.7_x64\cae_library\synthesis\verilog\ecp5u.v"
@I::"D:\software\diamond\3.7_x64\cae_library\synthesis\verilog\pmi_def.v"
@I::"D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\pll.v"
Verilog syntax check successful!
File D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\pll.v changed - recompiling
Selecting top level module pll
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\software\diamond\3.7_x64\cae_library\synthesis\verilog\ecp5u.v:757:7:757:10:@N:CG364:@XP_MSG">ecp5u.v(757)</a><!@TM:1471584041> | Synthesizing module VHI.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\software\diamond\3.7_x64\cae_library\synthesis\verilog\ecp5u.v:761:7:761:10:@N:CG364:@XP_MSG">ecp5u.v(761)</a><!@TM:1471584041> | Synthesizing module VLO.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\software\diamond\3.7_x64\cae_library\synthesis\verilog\ecp5u.v:1696:7:1696:14:@N:CG364:@XP_MSG">ecp5u.v(1696)</a><!@TM:1471584041> | Synthesizing module EHXPLLL.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\pll.v:8:7:8:10:@N:CG364:@XP_MSG">pll.v(8)</a><!@TM:1471584041> | Synthesizing module pll.

<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\pll.v:25:8:25:22:@W:CL168:@XP_MSG">pll.v(25)</a><!@TM:1471584041> | Pruning instance scuba_vhi_inst -- not in use ...</font>


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Aug 19 13:20:41 2016

###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015</a>
@N: : <!@TM:1471584041> | Running in 64-bit mode 
File D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Aug 19 13:20:41 2016

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Aug 19 13:20:41 2016

###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015</a>
@N: : <!@TM:1471584042> | Running in 64-bit mode 
File D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\synwork\pll_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Aug 19 13:20:42 2016

###########################################################]
Pre-mapping Report

<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\pll.fdc
@L: D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\pll_scck.rpt 
Printing clock  summary report in "D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\pll_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471584043> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1471584043> | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=32  set on top level netlist pll

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)



<a name=mapperReport6></a>Clock Summary</a>
*****************

Start      Requested     Requested     Clock      Clock          
Clock      Frequency     Period        Type       Group          
-----------------------------------------------------------------
System     100.0 MHz     10.000        system     system_clkgroup
=================================================================

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 13:20:43 2016

###########################################################]
Map & Optimize Report

<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471584129> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1471584129> | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1471584129> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)



@S |Clock Optimization Summary


<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks



##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 140MB)

Writing Analyst data base D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\synwork\pll_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1471584129> | Writing EDF file: D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\pll.edn 
K-2015.09L-2
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1471584129> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

Writing Verilog Simulation files

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

Writing VHDL Simulation files

Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)


Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)

<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\customers\highglass\latticefpga - 0818\ecp5_lvds\pll\pll.v:61:12:61:21:@W:MT246:@XP_MSG">pll.v(61)</a><!@TM:1471584129> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Fri Aug 19 13:22:08 2016
#


Top view:               pll
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\pll.fdc
                       
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1471584129> | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1471584129> | Clock constraints cover only FF-to-FF paths associated with the clock. 



<a name=performanceSummary10></a>Performance Summary</a>
*******************


Worst slack in design: 10.000

@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1471584129> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
                   Requested     Estimated     Requested     Estimated                Clock      Clock          
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
----------------------------------------------------------------------------------------------------------------
System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
================================================================================================================
@N:<a href="@N:MT582:@XP_HELP">MT582</a> : <!@TM:1471584129> | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 





<a name=clockRelationships11></a>Clock Relationships</a>
*******************

Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo12></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport13></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************

              Starting                                      Arrival           
Instance      Reference     Type        Pin       Net       Time        Slack 
              Clock                                                           
------------------------------------------------------------------------------
PLLInst_0     System        EHXPLLL     CLKOS     CLKOS     0.000       10.000
==============================================================================


<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************

              Starting                                      Required           
Instance      Reference     Type        Pin       Net       Time         Slack 
              Clock                                                            
-------------------------------------------------------------------------------
PLLInst_0     System        EHXPLLL     CLKFB     CLKOS     10.000       10.000
===============================================================================



<a name=worstPaths16></a>Worst Path Information</a>
<a href="D:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\pll.srr:srsfD:\customers\Highglass\LatticeFPGA - 0818\ecp5_lvds\pll\syn_results\pll.srs:fp:17221:17470:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      0.000
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     10.000

    Number of logic level(s):                0
    Starting point:                          PLLInst_0 / CLKOS
    Ending point:                            PLLInst_0 / CLKFB
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                 Pin       Pin               Arrival     No. of    
Name               Type        Name      Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
PLLInst_0          EHXPLLL     CLKOS     Out     0.000     0.000       -         
CLKOS              Net         -         -       -         -           2         
PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
=================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)


Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)

---------------------------------------
<a name=resourceUsage17></a>Resource Usage Report</a>
Part: lfe5u_12f-6

Register bits: 0 of 12096 (0%)
PIC Latch:       0
I/O cells:       0


Details:
GSR:            1
PUR:            1
VHI:            1
VLO:            1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 52MB peak: 143MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 13:22:08 2016

###########################################################]

</pre></samp></body></html>
